Size reduction designs have worked without error for a limited number of circuit types. Analysis of the mathematical design algorithms can locate problems in the approach. Relaxed hierarchical reduction approaches the problem by analyzing the overall circuit for errors, then the sub circuits that are contained within.
Current models (February 2011) of transistor circuits fail to estimate the drain or loss of power from the circuits involved and grounds necessary for safe system operation. The efficient operation of the overall circuit can only be obtained by overestimating the power needed. This reduces efficiency.
Models of power grids have used the transistor as the source of the current. This is not an efficient method, although it is simple. By replacing algorithms for the overall system with equations for each switch, efficiency of the system improved.