Apply a clock signal (a square wave with a 50 percent duty cycle) to the clock input of the shift register at a fixed frequency that is below the maximum clock frequency specification for the shift register.
Divide the "shift register clock frequency" by two and use this result for the frequency of the digital data stream. Generate the digital data stream signal with a waveform generator that is set to produce square waves at this calculated digital data stream frequency. Apply the digital data stream from the waveform generator to the serial input of the latching shift register.
Divide the shift register clock frequency by the number of shift register flip-flops used (most latching integrated circuits have 8 or 16 flop-flops that are connected directly to the input of 8 or 16 latches). Call this frequency the "latch clock frequency."
Delay the "latch clock frequency" (using a waveform generator or a delay circuit in the path of the latch clock line) to assure the latch clock pulses arrive after the register clock pulses. Set this delay time (shift clock to latch clock time) such that the time is longer than the "data-to-clock" delay specification for the shift register's flip-flops but shorter than one-half of the period of the "shift register clock frequency" used (divide 1 by the "shift register clock frequency" to obtain the period of the"shift register clock frequency").